1. Field of the Invention
The present invention relates generally to integrated circuit devices and, more specifically to an integrated circuit device that includes self-testing, fault-tolerant electronic and optoelectronic circuit components that are suitable for hardware reduction utilizing wafer-scale integration techniques. The integrated circuit device of the present invention also includes a high-speed optoelectronic interface to an axial optical data bus used to provide optical interconnectivity between the integrated circuit device components and other external devices.
2. Description of the Prior Art
Conventionally, the manufacture of integrated circuits is accomplished by simultaneously fabricating a plurality of identical circuits on a single wafer. The wafer is later scribed into a plurality of chips that are separately packaged and later integrated into a larger system. The total cost of such a system includes costs associated with the packaging of each individual chip and any costs associated with the increase in the system bulk because packaged chips are substantially larger than the chips themselves. And, the larger and more integrated a system becomes the greater the cost. For example, spacecraft avionics systems are large integrated systems having circuits built from conventional electronic chips and components. The chips are produced and packaged by many different manufacturers and therefore, the circuits are typically much larger than is necessary to perform each circuit""s intended function. These packaged chips may be placed into several spacecraft avionics units where each unit contains a specific function required for the given spacecraft system. The number of spacecraft avionics units required for a particular system is typically large and the units may require harness (wire cable) interconnections that are mounted onto the spacecraft structure. The quantity, size, and interconnections required of such units necessitates spreading the units over a large physical area, thereby, preventing satellites or similar spacecraft from being compact and lightweight structures.
Wafer-scale integration has been described in the art as a method for alleviating individual chip packaging and integration by including all of the processing required for a particular function in a single integrated circuit formed on a single semiconductor wafer. It has further been described in the art as a means for meeting the demands of high-speed processing since, by including all of the processing means of a particular application in a single integrated circuit, short and high-speed interconnections may be formed. However, wafer-scale integration is not without its disadvantages since defects due to the presence of impurities in the semiconductor crystal structure can occur and such defects can prevent individual circuit components located on the area of the defect from functioning properly. The larger the surface area of the wafer, the greater the number of defects; therefore, the ability to increase the wafer size to accommodate larger and larger systems is obviated in the absence of a defect-free wafer.
Various means of detecting and bypassing wafer defects have been utilized to mitigate the effects that such defects have on wafer-scale integrated circuits. Generally, the if operative circuits or devices on a wafer are electrically isolated from the inoperative devices through the use of discretionary connections. For example, U.S. Pat. No. 5,514,884 discloses a method of using multiple identical blocks of addressable circuitry that are tested prior to interconnection to compensate for the defects in a wafer-size integrated circuit. The multiple identical blocks of circuit elements and multiple identical blocks of control logic are provided on a wafer where both the blocks of circuit elements and the blocks of control logic are small enough that blocks found to be defective can be discarded without significantly reducing the size of the device. U.S. Pat. No. 5,274,264 discloses a defect tolerant power distribution network for wafer-scale integrated circuits, and a method for detecting and removing short circuits from the network. Portions of the conductive lines in the power distribution network are fabricated with an area whose width is reduced relative to the remainder of the line. The amount of reduction in the line is sufficient to produce a hot spot in response to current flow to a short circuit that is located at an electrically downstream location on the line. Upon locating the hot spot as being associated with a specific circuit, the shorted circuit is removed from the remainder of the network by such means as laser cutting. U.S. Pat. Nos. 5,498,886 and 5,576,554 disclose forming a plurality of circuit modules on a wafer and grouping the modules into blocks arranged on a rectangular grid. An interconnect network including signal lines and power lines, each with built-in redundancy, surrounds each block. Each module and each segment of the interconnect network are tested and, by using fusible links, the defect-free segments of the interconnect network are connected to the functional circuit modules. U.S. Pat. No. 5,430,734 discloses an integrated circuit device that includes a wafer containing dynamically configurable gate arrays. The device provides a fault-tolerant design that addresses manufacturing defects by mapping all defective gate arrays and defective portions of each gate array on the wafer. Such defect mapping occurs during initial wafer testing following the wafer fabrication and the mapping information is later used to program the desired wafer functions to exclude defective portions of the wafer. U.S. Pat. No. 5,140,189 discloses creating externally formed connections to a wafer-scale semiconductor device to avoid wafer level defects located at various sites on the wafer. In particular, small external shorting blocks or patch circuits are utilized to define spare sites that may be used as replacement sites for defective primary sites. The patch circuit is used in combination with a decoder circuit that is coupled to a predetermined number of spare sites on a fully processed wafer-scale integrated (WSI) wafer. The decoder contains one enabling output for each spare site so that connections completed by the shorting block or patch circuit can assign a logical address for a defective primary site to a designated spare site. Control circuits also exist in the wafer to electrically remove one or more defective primary sites and to activate a required number of spare sites that operate as replacement sites for the defective primary sites. U.S. Pat. No. 5,084,838 discloses a plurality of integrated circuits mounted on a large-scale integrated circuit device that are each provided with a bypass circuit that selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, all unit integrated circuits that are judged to be normal among a plurality of unit integrated circuits disposed along one row are coupled together.
To avoid testing individual circuits and manually connecting circuits to bypass defective circuit components, U.S. Pat. No. 5,287,345 discloses an array of interconnected node units formed as an integrated circuit on a semiconductor wafer for use in data handling, data processing or data storage. Each node unit includes a controlled switch for routing signal packets to destination node units whose addresses are included in the packets and also includes an automatic self-test function that, following satisfactory completion of the self-test, transmits a signal to adjacent node units that it is functioning properly. The controller of a node unit switch stores datum concerning which adjacent node units are defective and directs signal packets on paths around the defective node units.
Notwithstanding that defect avoidance techniques, like those previously described, may be necessary to produce operative wafer-scale integrated circuits, such techniques may not, by themselves, be acceptable for wafer-scale integration that meets the demands of applications requiring increased processing speed and performance, as well as increased integration density of microelectronic components. Such applications, e.g. avionics systems and other similarly larger and complex systems, could potentially require considerably large wafers. And, as previously described, increases in wafer size (or wafer surface area) are accompanied by proportional increases in the number of wafer defects. Therefore, the number and complexity of constructs used to mitigate such defects must likewise be increased. As a result, practical limitations on the size of single wafers may be necessary to avoid sacrificing wafer yield and processing efficiency.
What is needed, therefore, is a wafer-scale integrated circuit device that can utilize a built in capacity to self-test for defect induced circuit failure conditions and accommodate a means for the complete repair of the integrated circuit device and, further provide a high-speed data communication interface to external devices, e.g. other similar wafer-scale integrated circuit devices, to enable the functions of large-scale systems that are not assumable by a single wafer-scale integrated circuit device to be distributed among multiple such devices without sacrificing speed and processing efficiency.
The preceding and other shortcomings of the prior art are addressed and overcome by the present invention that provides an integrated circuit device. The device includes a wafer having a first surface, a second surface opposite the first surface, an optical transmission interface extending from the first wafer surface through to the second wafer surface, a semiconductor layer disposed on the first wafer surface, and a plurality of integrated circuits formed on the semiconductor layer. An optical data bus extends through the optical transmission interface normal to the first wafer surface and a plurality of devices are coupled to the optical data bus. To provide optical coupling between the plurality of integrated circuits and the optical data bus, a node is formed on the semiconductor layer adjacent to the optical transmission interface. Alternatively, the foregoing optical transmission interfaces may be omitted and the node formed at an edge of the wafer such that the optical data bus is extended along the edge of the wafer normal to the first wafer surface, defining a different optical interface.
In an alternate embodiment of the present invention, an integrated circuit device is provided that includes a plurality of adjacently stacked wafers, each wafer having a first surface, a second surface opposite the first surface and an optical transmission interface extending from the first surface through to the second surface, a semiconductor layer disposed on each first water surface, and a plurality of integrated circuits formed on each semiconductor layer. The plurality of integrated circuits include a node formed on the semiconductor layer adjacent to the optical transmission interface to couple optical data into and out of the plurality of integrated circuits. An optical data bus is included for coupling optical data between one wafer node and other nodes of wafers within the stack. The optical data bus extends axially through each of the optical transmission interfaces normal to each first wafer surface at each node. Alternatively, the foregoing type of optical transmission interfaces may be omitted and the nodes formed at an edge of each wafer such that the optical data bus extends along the edge of each wafer normal to each of the first wafer surfaces to form different interfaces therebetween. The integrated circuit device also includes the capability to replace defective wafers found in the stack of wafers.